MCS-012
Computer Organization and Assembly Language Programming.
January 2016 Session
Q - 1
(a)
Ans (i) : Add -128 and 120
2’s Complement of -128 is
First binary conversion of 128 is 1000 0000 which requires 8 bits of information and
In this example the maximum size for -128 is 8 bits but including sign bit.
For storing -128 sign bit 1 is required with the given magnitude.
And hence addition of -128 and 120 is not possible.
Ans (ii) : Subtract 124 from -99
The binary conversion of 124 is 0111 1100 so 2’s complement is 10000100
The Binary conversion of -99 is 1110 0011 so 2’s complement is 00011101
In Binary, Subtraction is not done directly it is done by taking a MINUS sign for a positive number. For subtraction changing +124 to -124.
-99 00011101
-124 10000100
-------------------------
-223 1 0010 0001
For storing answer it will requires 9th bit extra, so we can say it will be overflow.
Ans (iii): Add 64 and 61
Sign bit is 0 because 64 and 61 are positive numbers and magnitude of 7 bits is here.
The Binary Conversion of 64 is 0100 0000 so 2’s complement is 1100 0000
And Binary Conversion of 61 is 0011 1101 so 2’s complement is 1100 0011
1100 0000
1100 0011
11000 0011
Requires carry bit extra hance the answer of this sum is overflow.
(b) Convert Hexadecimal number
FAEBDC
Dec Hex Bin Dec Hex Bin Dec Hex Bin Dec Hex Bin
0 0 0000 4 4 0100 8 8 1000 12 C 1100
1 1 0001 5 5 0101 9 9 1001 13 D 1101
2 2 0010 6 6 0110 10 A 1010 14 E 1110
3 3 0011 7 7 0111 11 B 1011 15 F 1111
F A E B D C Hex
111110101110101111011100 Binary
Decimal Conversion
FAEBDC
=15X165+10X164+14X163+11X162+13X161+12X160
=15 X 1048576 + 10 X 65536 + 14 X 4096 + 11 X 256 + 13 X 16 + 12 X 1
=15728640 + 655360 + 57344 + 2816 + 208 + 12
=(16444380)10
Octal Number Conversion
=(76565734)8
(c) Convert the following string into equivalent “UTF 16” code-
“You may assume that Hindi swar starts with a”
Are these UTF 16 codes similar as that used in ASCII?
UTF 16 Stands for Universal Character Set Transformation Format 16
– 16-bits (216 =512 characters)
“UTF 16” Codes: Y=087 o=079 u=085 (space) =032 m=109 a=097 y=121 (space) =032 (space) =032 t=116 h=104 a=097 t=116 (space) =032 H=072 i=105 n=110 d=100 i=105 (space) =032 s=115 w=119 a=097 r=114 (space) =032 s=115 t=116 a=097 r=114 t=116 s=115 (space) =032 w=119 i=105 t=116 h=104 (space) =032 अ (hindiswar)= < 255 (will be in the Extended list between 256 – 511)
Ans (d) :
Karnugh’s Map
If first and fourth bit is same then 0 else 1.
A
|
B
|
C
|
D
|
Result
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
0
|
1
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
1
|
0
|
K Map Table
00
|
01
|
11
|
10
| |
00
|
0
|
1
|
1
|
0
|
01
|
0
|
1
|
1
|
0
|
11
|
1
|
0
|
0
|
1
|
10
|
1
|
0
|
0
|
1
|
Ans (e)
An 8 bit data 01101101 after transmission is received as 01001101. Explain how SEC code will detect and correct this problem.
The 8-bit Sent Data = 0110 1101
The 8-bit received Data = 0100 1101
SEC means Single Error Correction
Check with parity bits, before that Create a new parity bit with new data
P1= D1 D2 D4 D5 D7 = 01010 even parity will be 0 – correct
P2= D1 D3 D4 D6 D7= 00010 even parity will be 1 - incorrect
P3= D2 D3 D4 D8 = 1001 even parity will be 0 - incorrect
P4= D5 D6 D7 D8 = 1101 even parity will be 1 – correct
After Checking
We find that common data bit numbers are D3 & D4
But D4 is also present in P1that means error has been occurred in D3 only.
By this we detect error in D3 and Correct it by replacing it by 0 to 1.
Ans (f): Design a two bit counter (a sequential circuit) that counts from 00 to 10 only. Thus, the counter states are 00, 01, 10, 00, 01,…. You should show the state table, state diagram, the k-map for circuit design and logic diagram of the resultant design using D flip-flop or J-K flip flop.
Present State
|
Next State
|
Flip Flop State
| ||||
A
|
B
|
X
|
A
|
B
|
DA
|
DB
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
0
|
0
|
1
|
K Map for DA
00
|
01
|
11
|
10
| |
0
|
1
| |||
1
|
1
|
K Map for DB
00
|
01
|
11
|
10
| |
0
|
1
|
1
| ||
1
|
1
|
Single Precision
1bit = sign bit
7 bits = Exponent Bits
24 bits = Mantissa Bits
Sign bit is: 0
124 = 1111100
0.0625 = 0001
Number (124.0625)10 = (1111100.0001)2 Convert Binary number to Exponent Form
1111100.0001 Will be 1.1111000001 * 26 Discard 1.
Significant number = (1111000001)2
Exponent = 127+6=132
Exponent number (132)10 = (10000100)2
Single Precision Representation
0000010011110000010000000000000
Double Precision
1 bit = Sign Bit
10 bits = Exponent Bits
53 bits = Mantissa Bits
Sign bit is: 0
124 = 1111100
0.0625 = 0001
Number (124.0625)10 = (1111100.0001)2 Convert Binary number to Exponent Form
1111100.0001 Will be 1.1111000001 * 26 Discard 1.
Significant number = (1111000001)2
Exponent = 1023+6=1029
Exponent number (1029)10 = (10000000101)2
Single Precision Representation
0000000010111110000010000000000000000000000000000000000000000000
Question 2.
A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only
A 32 × 4 RAM means that RAM has 32 words,
5 address lines (25 = 32), and 4 bit data word size. We can represent a RAM using 2A×D,
Where
A-> Number of address lines
D -> Number of Data lines
The 32 × 4 RAM circuit where 5 × 32 bit decoder is used
The 4 bit data input come from input buffer
The 4-bit data output is stored in output buffer
A RAM has a capacity of 8192K having the word size of 16 bits and supports byte addresses only.
(i) How many data input and output lines does this RAM need? Explain your answer.
Ans: Data input and Data output lines are equal and of word size, Hence Ram will need 16 Data lines
(ii) How many address lines will be needed for this RAM? Explain.
Ans: Convert 8192K to 2A × (D/2) format supports byte addresses only 8192K/8 = (8192 * 1024) / 8 = (213 * 210) / 23 =223-3 =213 We can represent a RAM using 2A × (D/2) = 213 × (16/2) RAM Hence Address lines are 13 Address lines.
(b) A computer has 1MB RAM and has word size of 16 bits. It has cache memory having 16 blocks with a block size of 32 bits. Explain how a main memory address will be mapped to a cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii) Two way set associative mapping scheme is used.
Main memory Size = 1 MB (RAM)
Convert it to Words if word size is 16 bits Main memory Size = 65536 Words
Main Memory word size = 16 bits
Cache Memory Size = 16 Blocks
Cache Memory Block size = 32 bits
⇒1 Block of Cache = 2 Words of RAM
⇒Assume Memory location address 520 is equivalent to Block address 260.
⇒ Total number of possible Blocks in Main Memory
= 65536 /2
= 32768 blocks
Associative Mapping: The block can be anywhere in the cache.
Direct Mapping: Size of Cache = 16 blocks
Location of Block 260 in Cache =
260 modulo 16 = 4
2 Way set associative mapping: Number of blocks in a set = 2
Number of sets =
Size of Cache in blocks / Number of blocks in a set
= 32768 / 2
= 16384
Block 260 will be located anywhere in (260 modulo 8) set, that is set 4.
(d) Explain the term FAT in the context of disk operating system. What will be the size of a disk and it’s FAT, if a disk has 64 tracks with each track having 16 sectors and size of each sector is 512 byte? You may take the cluster size as 4 sectors.
Given: Disk has 64 tracks Track has 16 sectors Sector is 512 byte (0.5 KB) Cluster size as 4 sectors
Find:
Track Size (in KB) = No. of Sector x No. of Btyes
= 16 * 0.5 KB
= 8 KB
Cluster Size (in KB) = No. of Track x No. of Sector
= 64 * 8 KB
= 512 KB
Disk Size (in KB) = No. of Cluster x No. of Track
= 4 * 512 KB
= 2048 KB
=2MB
FAT (or FAT entries) = Disk Size (or Disk Capacity) / Cluster Size
= (2 * 1024 * 1024) / (2 * 1024)
= (2 * 1024 * 1024) / (2 * 1024)
= 1024 No. of entries
Note: FAT contains vital information; two copies of FAT are stored on the disk, so that in case one gets destroyed, the other can be used (Acutual entries = 1024 entries / 2 = 512 entries).
Question 3.
(a) A hypothetical machine has 22 registers. Out of these 6 registers are used as segment registers. Assume that the machine uses segment registers to find physical address in the similar way as is done in 8086 processor. Remaining 16 registers are general purpose registers. All the registers and memory word for the machine are of 16 bits. The machine has 1 M Word RAM. An instruction of the machine is of 32 bits which includes opcode – 5 bits, addressing mode specification – 3 bits and remaining bits for specifying the operand addresses. Each instruction contains at most two operand addresses – at most one memory operand and remaining register operand(s). What would be the size of memory address, if direct addressing is used? What would be the size of the direct register operand? The machine is to be used for calculations involving arrays and floating point numbers. Design five different types of addressing modes for this machine. Give justification of the selection of every addressing mode. Total general purpose registers = 32
All Register equal size = 16 bits
Registers used as stack for subroutine calls = 16
Main memory = 1 M Word
Memory word size = 16 bits
Instructions size = one memory word = 16 bits
Opcode = 5 bits
Addressing mode = 3 bits
Remaining bits = operand addresses
Please note the following points:
§ The opcode size is 5 bits. So, in general it will have 25 = 16 operations. §
There is three operand address machine. §
There are two bits for addressing modes.
Therefore, there are 23 = 6 different addressing modes possible for this machine. §
The last field (8 – 32 bits = 24 bits) here is the operands or the addresses of operands field.
IMMEDIATE addressing mode:
In case of immediate operand the maximum size of the unsigned operand would be 210
DIRECT addressing mode:
In case it is an address of operand in memory, then the maximum physical memory size supported by this machine is 210 = 1 KB.
REGISTER addressing mode:
There are 64 general purpose registers. Therefore, there is 64 = 26 (6-bits for Register address)
REGISTER INDIRECT addressing mode:
Assume that the machine as stated in part (a) has named 5 of its general purpose registers based on their possible role in instruction execution as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Instruction Register (IR) , Data Register (DR) and Flag registers (FR). To execute an instruction of the machine that has a direct memory operand and a register operand, the memory operand is first brought into the DR register and the register operand is transferred to AC register. The result of the operation is stored in the AC register. One of the instructions of the machine is given below: ADD R1, X // this instruction adds the operand stored in Register R1 and memory location X. The result is stored in the AC register. Write and explain the sequence of micro-operations that are required to fetch and execute this instruction. Make and state suitable assumptions, if any. STORE memAddress // this instruction result in storage of the content of AC register into the memory location specified by memAddress. Write and explain the sequence of micro-operations that are required to fetch and execute this instruction Make and state suitable assumptions, if any.
The instruction execution using the micro-operations requires:
§
Instruction fetch:
fetching the instruction from the memory. §
Instruction decode:
decode the instruction. §
Operand address calculation:
find out the effective address of the operands. §
Execution:
execute the instruction. §
Interrupt Acknowledge:
perform an interrupt acknowledge cycle if an interrupt request is pending.
(C) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 1010 0011 and 1100 1011 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above).
(i) Subtraction of R1 and R2
(ii) AND of R1 and R2
(iii) Shift right R2 twice
(iv) Add of R1 and R2 with carry
(e)Explain the working of the instruction pipelining, with the help of a diagram.
To extract better performance instruction execution can be done through instruction pipeline. The instruction pipelining involves decomposing of an instruction execution to a number of pipeline stages.
Some of the common pipeline stages can be instruction fetch (IF), instruction decode (ID), operand fetch (OF), execute (EX), store results (SR).
An instruction pipe may involve any combination of such stages. A major design decision here is that the instruction stages should be of equal execution time. The reason why it should be is,
A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an instruction the following may be a scenario of execution.
A pipeline allows overlapped execution of instructions. Thus, during the course of execution of an instruction the following may be a scenario of execution.
Please note the following observations about the above figure: § The pipeline stages are like steps. Thus, a step of the pipeline is to be complete in a time slot. The size of the time slot will be governed by the stage taking maximum time. Thus, if the time taken in various stages is almost similar, we get the best results. § The first instruction execution is completed on completion of 5th time slot, but afterwards, in each time slot the next instruction gets executed. So, in ideal conditions one instruction is executed in the pipeline in each time slot. § After the 5th time slot and afterwards the pipe is full. In the 5th time slot the stages of execution of five instructions are: SR (instruction 1) (Requires memory reference)
EX (instruction 2) (No memory reference)
OF (instruction 3) (Requires memory reference)
ID (instruction 4) (No memory reference)
IF (instruction 5) (Requires memory reference)
(f)Assume that a RISC machine has 128 registers out of which 16 registers are reserved for the Global variables and 16 for Instruction related tasks. This machine has been designed to have 12 registers for storing four input parameters, four output parameters and four local variables for a subroutine call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for procedure calls. You must explain how the parameters will be passed, if a subroutine calls another subroutine.
Assumptions: Register file contains 128 registers. Let them be called by register number 0 – 127. The table shows the use of registers: when there is call to function A (fA) which calls function B (fB) and function B calls function C (fC).
§ Global registers which are shareable by all functions. § Parameters registers for holding parameters passed from the previous function to the current function. They also hold the results that are to be passed back. § Local registers that hold the local variables, as assigned by the compiler. § Temporary registers: They are physically the same as the parameter registers at the next level. This overlap permits parameter passing without the actual movement of data. The register buffer is filled as function A called function B, function B called function C, function C called function D. The function D is the current function. The current window pointer (CWP) points to the register window of the most recent function (i.e. D). Any register references by a machine instruction is added with the contents of this pointer to determine the actual physical registers. On the other hand the saved window pointer identifies the window most recently saved in memory. This action will be needed if a further call is made and there is no space for that call. If function D now calls function E arguments for function E are placed in D’s temporary registers indicated by D temp and the CWP is advanced by one window.
Figure:- circular overlapping windows
If function E now makes a call to function F, the call cannot be made with the current status of the buffer, unless we free space equivalent to exactly one window. This condition can easily be determined as current window pointer on incrementing will be equal to saved window pointer. Now, we need to create space. The simplest way will be to swap FA register to memory and use that space. Thus, an N window register file can support N –1 level of function calls.
Question 4
(a)Write a program in 8086 assembly Language (with proper comments) to count the number of alphabets ‘a’, ‘e’ and ‘o’ (irrespective of lower or upper case) in a strings. For example, in case the strings is: “ABaDEFeHIO” the count of ‘a’ will be 2, ‘e’ is 2 and ‘o’ is 1. You may assume that string is available in the memory and is of length 10. Make suitable assumptions, if any.
OUTPUT :
Count of A’s is 2
Count of E’s is 2
Count of O’s is 1
(B)Write a program in 8086 assembly language that accepts a 2 digit input from the keyboard (as ASCII input) into packed BCD number. The packed BCD number may be stored in memory.
OUTPUT
Enter Number : 23
DIGIT1 : 02h
DIGIT2 : 03h
BCD : 35h
(C)Write a simple near procedure in 8086 assembly language that receives an ASCII digit as parameter. It returns 1 if the ASCII digit is ‘Z’ else it returns 0. Make suitable assumptions, if any.
OUTPUT :
ENTER ALPHABET ‘Z’ : B
BIT RETURNED IS : 0
Some Figures are missing in this Assignment.
In Comments PUT Your Email ID to Receive the original Images who have the solution.
Thank you,
Hitesh Vataliya.
http://www.vataliyatuitionclasses.com
Near Yash Complex,
Gotri, Vadodara - 390021
Gujarat, India.
Contact No: +91 9726185104
FOR MORE INFORMATION :
Visit Our Center :
120-121, Gangotri Complex,
30 Meter Gotri Road,Near Yash Complex,
Gotri, Vadodara - 390021
Gujarat, India.
Contact No: +91 9726185104
No comments:
Post a Comment